Column: From 3D NAND to 3D DRAM — how vertical stacking is reshaping memory chip manufacturing

DIGITIMESOctober 13, 2026en

After 2013, planar NAND flash memory began reaching its scaling limits at the 15–16nm process node. Capacitive coupling between the floating gates of adjacent memory cells increasingly disrupted their threshold voltages, making stored data harder to read reliably. The problem became particularly acute with the adoption of triple-level cell (TLC) NAND, which requires precise threshold-voltage detection. Changes in the charge stored by neighbouring cells could alter those voltages, making further planar scaling increasingly difficult.

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